Memory cell structure, method of manufacturing a memory, and memory apparatus

ABSTRACT

The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. 
     A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

TECHNICAL FIELD

The present disclosure relates to a memory cell structure, a method ofmanufacturing a memory having the memory cell structure, and a memoryapparatus.

Patent Document 1: Japanese Patent Application Laid-open No. 2002-329846

BACKGROUND ART

Along the significant advancement of various information devices rangingfrom mobile terminals to high-capacity servers, further higherperformance, i.e., high-degree of integration, high speed, and low powerconsumption are pursued also in elements such as memories and logicsconstituting those devices. In particular, the progress of semiconductornonvolatile memories is striking, and a flash memory as a high-capacityfile memory is increasingly prevailing while increasing momentum ofovertaking a hard disk drive. On the other hand, in order to aim atdevelopment to a code storage or working memory and replace a NOR flashmemory, a DRAM, and the like currently widely used, a FeRAM(Ferroelectric Random Access Memory), an MRAM (Magnetic Random AccessMemory), a PCRAM (Phase-Change Random Access Memory), and the like arein the process of being developed. Some of them are already put intopractical use.

Among those memories, the MRAM stores data depending on a magnetizationdirection of a magnetic body and thus enables rewrite at high speed andalmost infinitely (10¹⁵ times or more). The MRAM is already used in thefields of industrial automation, aircraft, and the like. The MRAM isexpected to be developed in a code storage or working memory in thefuture because of its high-speed operation and reliability.

In recent years, in contrast to magnetic storage of a horizontalmagnetic type, a perpendicular magnetic type that is suitable forreduction in area of a memory cell has been proposed. Due toresponsiveness of data access (write/read) and being a nonvolatile RAM,a demand for replacement of a DRAM is conceived, but it is indispensableto reduce the size of a memory cell that is comparable to the DRAM, thatis, reduce a bit unit price.

The MRAM is similar to a DRAM in the structure as a semiconductormemory, and has such a shape that a capacitor portion in the DRAM isreplaced with an MTJ (Magnetic Tunnel Junction) element.

In the structure of the MRAM already mass-produced, a transistor forselecting each MTJ, a bit line, a word line, an MTJ, and a data line arelaminated on a substrate in the stated order from the bottom. In otherwords, the MTJ is disposed on the almost uppermost layer of the element,and the word line and the bit line are formed as memory connecting wiresin laminated wiring between elements, which is a second-half step (BackEnd Of Line) of semiconductor manufacturing. In the structure, after thememory connecting wires are formed, an MTJ to be a memory element islaminated on those connecting wires, and data line is then formed.

Specifically, the structure in which components from an accesstransistor (field-effect transistor) to an MTJ are drawn to the vicinityof the uppermost layer of the metal wires and then connected is themainstream. In this case, since the bit line and the word line are drawnto the MTJ, the resistance of the bit line and the word line becomeslarge, and thus a current for rewriting the memory content of the MTJcannot be increased. This becomes a problem in terms of current control.As one of methods for solving this problem, an attempt to make aperpendicular-type access transistor is performed (see Patent Document1).

SUMMARY OF INVENTION Problem to be Solved by the Invention

Incidentally, in the semiconductor structure of the MRAM, there is ademand to reduce the magnitude of wiring resistance of the bit line andthe word line as much as possible. Further, the MRAM has a data line,which does not exist in the DRAM. So, if a data line is wired in amemory element, it is necessary to prevent the area of the memoryelement from being increased as much as possible. Additionally, the heatresistance of the MTJ is a problem. In other words, heat treatment inwiring of the word line and the like may cause performance degradationof the MTJ. This is required to be avoided.

In this regard, it is an object of the present disclosure to provide amemory cell structure of an MRAM, which reduces resistance of drawnwiring to be connected to an MTJ as a memory element, increases acurrent provided to the memory element, reduces an area of a memorycell, and also avoids performance degradation of the MTJ due to heat.

Means for Solving the Problem

First, according to the present disclosure, there is provided a memorycell structure including: a transistor that uses a first diffusion layerformed in a bottom portion of a concave portion formed by processing asilicon substrate into a groove shape, and a second diffusion layerformed in upper end portions of two opposing sidewall portions of theconcave portion, to form channels at portions between the firstdiffusion layer and the second diffusion layer in the two sidewallportions; and a memory element that is disposed below the firstdiffusion layer, the first diffusion layer being electrically connectedto the memory element via a contact formed after the silicon substrateis thinned.

In such a manner, since the two opposing sidewalls of the concaveportion are used as channels, the channel width more than twice as largeas a normal transistor can be ensured. Additionally, since the memoryelement is disposed below the first diffusion layer, the formation ofthe memory element can be performed after the formation of metal wires.

Second, in the above-mentioned memory cell structure according to thepresent disclosure, it is desirable that the first diffusion layer beelectrically insulated by an insulating film and a substrateconcentration profile for each memory cell.

In such a manner, since electrical isolation is provided by theinsulating film and the substrate concentration profile, an operationfailure does not occur.

Third, in the above-mentioned memory cell structure according to thepresent disclosure, it is desirable that the contact have a structureinsulated from the silicon substrate.

In such a manner, since the contact has a structure insulated from thesilicon substrate, an operation failure does not occur.

Fourth, in the above-mentioned memory cell structure according to thepresent disclosure, the silicon substrate can be an SOI (silicon oninsulator) substrate.

In such a manner, since the silicon substrate is an SOI substrate, RIE(Reactive Ion Etching) can be stopped at high accuracy at apredetermined position of the silicon substrate, and a forming processcan be made more reliable and stable.

Fifth, in the above-mentioned memory cell structure according to thepresent disclosure, it is desirable that the memory element be an MTJ(Magnetic Tunnel Junction) element. This realizes a memory cellstructure that is suitable in an MRAM using an MTJ element.

According to the present disclosure, first, there is provided a methodof manufacturing a memory having a memory cell structure including atransistor and a memory element, the transistor using a first diffusionlayer formed in a bottom portion of a concave portion formed byprocessing a silicon substrate into a groove shape, and a seconddiffusion layer formed in upper end portions of two opposing sidewallportions of the concave portion, to form channels at portions betweenthe first diffusion layer and the second diffusion layer in the twosidewall portions, the memory element being disposed below the firstdiffusion layer, the first diffusion layer being electrically connectedto the memory element via a contact formed after the silicon substrateis thinned, the method including the step of forming an intermediatelaminated body as a part of the memory cell structure by performing atleast the steps of: forming field isolation layers at a predetermineddepth of the silicon substrate; forming the groove-shaped concaveportion between the field isolation layers; forming the first diffusionlayer in the bottom portion of the concave portion; forming the seconddiffusion layer in the upper end portions of the sidewall portions ofthe concave portion; and forming a metal wire in an upper portion of thesecond diffusion layer.

In such a manner, since the step of forming a metal wire in an upperportion of the second diffusion layer is included, a connection from thetransistor to the memory element can be shortened.

Second, in the above-mentioned method of manufacturing a memory cellaccording to the present disclosure, it is desirable to include thesteps of: bonding another silicon substrate as a support substrate tothe silicon substrate on which the intermediate laminated body isformed; and thinning the silicon substrate.

In such a manner, since the step of bonding another silicon substrate asa support substrate to the silicon substrate is included, it is possibleto thin the silicon substrate and easily form a contact on the backsurface of the silicon substrate.

Third, in the above-mentioned method of manufacturing a memory cellaccording to the present disclosure, it is desirable to include the stepof forming a contact from the first diffusion layer formed on thethinned silicon substrate.

In such a manner, since the contact is formed from the bottom portion ofthe first diffusion layer on the back side, a distance between thetransistor and the memory element can be shortened.

Forth, in the above-mentioned method of manufacturing a memory cellaccording to the present disclosure, it is desirable to include the stepof forming a memory element electrically connected to the firstdiffusion layer by the contact. Thus, a structure required as a memorycell is formed.

According to the present disclosure, there is provided a memoryapparatus including: a memory cell including a memory element that holdsinformation depending on a magnetization state of a magnetic body; andtwo types of wires mutually intersect and other types of wires. Thememory cell has a memory cell structure including a transistor that usesa first diffusion layer formed in a bottom portion of a concave portionformed by processing a silicon substrate into a groove shape, and asecond diffusion layer formed in upper end portions of two opposingsidewall portions of the concave portion, to form channels at portionsbetween the first diffusion layer and the second diffusion layer in thetwo sidewall portions, and the memory element that is disposed below thefirst diffusion layer, the first diffusion layer being electricallyconnected to the memory element via a contact formed after the siliconsubstrate is thinned, the memory element being provided to a currentbetween the two types of wires via the transistor.

In this case, the transistor has the two opposing sidewalls of theconcave portion as channels, and thus the channel width more than twiceas large as a normal transistor can be ensured, and a memory apparatusincluding a memory cell with a high current capability can be formed.

Effects of the Invention

According to the present disclosure, since the connection from thetransistor to the memory element can be shortened, connection resistancecan be made small. Since the two opposing sidewalls of the concaveportion are used as channels, the channel width of the transistor isincreased. This can increase a current provided to the memory element,and also reduce an area of a memory cell.

Additionally, since the memory element can be formed after the metalwire is formed, the influence by heat treatment of the metal wire can besuppressed.

It should be noted that the effects described herein are not necessarilylimited and any effects described in the present disclosure may beproduced.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing a circuit configuration of a memory cell ofeach of an MRAM and a DRAM.

FIG. 2 is a diagram showing a structure of a top surface of the memorycell according to the embodiment.

FIG. 3 is a diagram showing a layer structure of the memory cellaccording to the embodiment.

FIG. 4 is a diagram showing a current flow when a transistor within thememory cell according to the embodiment is turned on.

FIG. 5 is a diagram showing a layer structure in a state where anisolation region of each cell of the memory cell according to theembodiment is formed.

FIG. 6 is a diagram showing a layer structure in a state where a concaveportion of the memory cell according to the embodiment is formed.

FIG. 7 is a diagram showing a layer structure in a state where a firstdiffusion layer of the memory cell according to the embodiment isformed.

FIG. 8 is a diagram showing a layer structure in a state whereprotective films are formed within the concave portion of the memorycell according to the embodiment.

FIG. 9 is a diagram showing a layer structure in a state where a gateelectrode is embedded in the memory cell according to the embodiment.

FIG. 10 is a diagram showing a layer structure in a state where a seconddiffusion layer of the memory cell according to the embodiment isformed.

FIG. 11 is a diagram showing a layer structure in a state where thesecond diffusion layer of the memory cell according to the embodimentand a bit line connected thereto are formed.

FIG. 12 is a diagram showing a layer structure in a state where metalwires of the memory cell according to the embodiment are formed.

FIG. 13 is a diagram schematically showing a procedure of bonding anintermediate laminated body formed on one substrate to another substrateand performing thinning so as to manufacture the memory cell accordingto the embodiment.

FIG. 14 is a diagram showing a layer structure in which a back contactis formed from the first diffusion layer of the intermediate laminatedbody of the memory cell according to the embodiment.

FIG. 15 is a diagram showing a layer structure in which insulatingprotective films are formed on sidewalls of the back contact formed fromthe first diffusion layer of an intermediate laminated area of thememory cell according to the embodiment.

FIG. 16 is a diagram showing a modified example of a memory cellstructure according to the embodiment.

MODE(S) FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present disclosure will be describedin the following order.

<1. Comparison between Circuits of MRAM and DRAM>

<2. Layout Design of Upper Portion of Memory Cell>

<3. Memory Cell Structure of Embodiment>

<4. Method of Manufacturing Memory Cell of Embodiment>

<5. Modified Example>

1. Circuit Configurations of MRAM and DRAM

First, circuit configurations of an MRAM and a DRAM will be describedwith reference to FIG. 1.

Part A of FIG. 1 shows a circuit configuration of a memory cell 1 of anMRAM. As shown in part A of FIG. 1, the memory cell 1 of the MRAM isconstituted by an MTJ element 3 (Rm), an access transistor 5, a wordline 2, a bit line 6, and a data line 4.

The MTJ element 3 has a function as a memory element for storinginformation. In general, the MTJ element 3 has a structure including twoferromagnetic and an insulating layer sandwiched therebetween.

Of the two ferromagnetic layers, magnetization of one ferromagneticlayer is fixed, and magnetization of the other ferromagnetic layer isvariable. A thin insulating layer as a barrier is located between theferromagnetic layers. A magnetization direction of the one magneticlayer is fixed and that of the other magnetic layer is changed, and dueto a difference between resistance values thereof, information is thusheld. When the two magnetic layers are different in magnetizationorientation, resistance is high, and when the two magnetic layers havethe same magnetization orientation, resistance is low. A current isprovided to the MTJ element 3 and detected, and thus memory content (1or 0) can be read.

The access transistor 5 plays a role of a switch on whether a current isprovided to the MTJ element 3 of each memory cell 1 or not. When theaccess transistor 5 is turned on, a current can be provided to the MTJelement 3. In other words, it is possible to access the MTJ element 3.When the access transistor 5 is turned off, a current can be stopped tobe provided to the MTJ element 3. In other words, it is possible tocancel the access to the MTJ element 3.

The word line 2 controls on and off of the access transistor 5. The wordline 2 is connected to a gate electrode of the access transistor 5. Whena voltage is applied to the word line 2, the voltage of the gateelectrode becomes constant and a corresponding access transistor 5 canthus be turned on.

The bit line 6 supplies a constant voltage to a source of the accesstransistor 5.

The data line 4 is connected to be paired with the bit line 6. This canmake a current path between the bit line 6 and the data line 4.

If the access transistor 5 is turned on, a current is provided betweenthe bit line 6 and the data line 4, and thus a constant current can beprovided to the MTJ element 3. This makes it possible to detect aresistance value of the MTJ element 3 and read memory content.Alternatively, when a spin current is provided, information can bewritten.

In contrast to this, as shown in part B of FIG. 1, a memory cell 10 of aDRAM has a circuit configuration constituted by a capacitor 7, an accesstransistor 5, a word line 2, and a bit line 6.

In this configuration, the MTJ element 3 of the memory cell 1 of theMRAM is replaced with the capacitor 7. Actually, the capacitor 7corresponds to a memory element, and information is stored depending onthe presence or absence of charge stored therein.

Further, a portion corresponding to the data line 4 is a plate. Theplate is a plate-shaped electrode and does not need to be wired as thedata line 4 in each memory cell 1 as in the MRAM. In other words, thisis advantageous in terms of reduction in memory cell size.

However, in lamination of the memory cell 1 of the MRAM, a wiring layerof the data line 4 has to be laminated without fail, and this isinconvenient in terms of reduction in memory size.

2. Layout of Upper Portion of Memory Cell

Hereinafter, a layout of the memory cell 1 of the MRAM according to theembodiment will be described with reference to FIG. 2. FIG. 2 is adiagram schematically showing a structure of a memory cell arrayaccording to the embodiment when viewed from the top. As shown in FIG.2, a plurality of word lines 2 is wired in a vertical direction and aplurality of bit lines 6 is wired in a lateral direction such that theword lines 2 and the bit lines 6 intersect mutually. The memory cell 1is provided at a center position of an intersection of the word line 2and the bit line 6. As shown in the figure, a feature size of the memorycell 1 is 2F×2F=4F2. In this embodiment, channels 12 of the accesstransistor 5 are formed on sidewalls of both sides of each word line 2.When the sidewalls of the both sides of the word line 2 running in thevertical direction are used as the channels 12, it is easy to earn aneffective channel width and ensure a current capability. In the figure,when a channel having each side of F is used on both sides, a channelwidth corresponding to 2F is earned.

In the case where the size of the memory cell 1 is extended in avertical direction with respect to the figure, it is possible to earn aneffective channel width of 3F in a memory cell size of 5F2 or 4F in amemory size of 6F2.

3. Memory Cell Structure of Embodiment

Hereinafter, a memory cell structure according to the embodiment and itsperipheral circuit portion will be described with reference to FIG. 3.FIG. 3 is a diagram showing a layer structure of the memory cellaccording to the embodiment. The memory cell 1 according to thisembodiment includes the MTJ element 3, the access transistor 5, the wordline 2, the bit line 6, and the data line 4. FIG. 3 shows a portion inwhich three memory cells 1 are formed.

In a silicon substrate 14, a concave portion 15 is formed into a grooveshape. In the concave portion 15, a gate electrode 18 is embedded. Thegate electrode 18 is connected to the word line 2 (not shown).

The access transistor 5 is constituted by a first diffusion layer 16, asecond diffusion layer 19, the gate electrode 18, and channels 12. Thefirst diffusion layer 16 corresponds to a drain of the access transistor5. Further, the second diffusion layer 19 corresponds to a sourcethereof.

As shown in the figure, the access transistor 5 has a configuration inwhich the first diffusion layer 16 is formed on the bottom portion ofthe portion 15 formed by processing the silicon substrate 14 to have agroove shape, the second diffusion layer 19 is formed on the upper endportions of two opposing sidewall portions of the concave portion 15,and the first diffusion layer 16 and the second diffusion layer 19 areused to form the channels 12 in the two sidewall portions at a portionbetween the first diffusion layer 16 and the second diffusion layer 19.

In such a manner, the second diffusion layer 19 is formed above thechannels 12, and the access transistor 5 has a source-drain path in aperpendicular direction.

On both sides of the first diffusion layer 16, field isolation layers 11made of a silicon oxide film or the like as a material are formed. Thus,the first diffusion layer 16 is isolated for each memory cell 1.

In the lower portion of the first diffusion layer 16, the siliconsubstrate 14 is thinned to form a back contact 27. The back contact 27is formed of a copper plug, a tungsten plug, or the like. It isdesirable that the back contact 27 be extracted at low resistance. Theback contact 27 has a relatively low aspect ratio and is directly drawnfrom the first diffusion layer 16, and thus resistance can be made about¼ to ⅕ lower than a general one.

Protective insulating films 29 are formed on both sides of the backcontact 27. Additionally, a substrate concentration profile of thesilicon substrate 14 is adjusted. This is also because electricalinsulation of the first diffusion layer 16 is obtained for each memorycell 1.

The MTJ element 3 is formed as a memory element on the lower portion ofthe back contact 27. A back insulating layer 28 is formed on both sidesof the MTJ element 3. The data line 4 is laminated below the lowerportion of the MTJ element 3. The lamination of the data line 4 isperformed after the MTJ element 3 is formed, and a process by low-heatprocessing is made possible. Thus, characteristic degradation of the MTJelement 3 due to heat can be avoided.

The data line 4 is disposed to be parallel to the bit line 6. Thisenables two lines to be collected to one side on a plane, and thus anincrease in cell area can be suppressed.

Here, a current flow in an operating state of the memory cell structurewill be described with reference to FIG. 4.

FIG. 4 shows a state where the leftmost access transistor 5 is turned onand the other transistors are turned off. As described above, the accesstransistor 5 is constituted by the first diffusion layer 16, the seconddiffusion layer 19, the gate electrode 18, and the channels 12. Turningthe access transistor 5 on means turning the gate electrode 18 on(applying a constant voltage), and thus a corresponding gate electrode18 is shown as ON. The other gate electrodes are shown as OFF. When thegate electrode is turned on, the channels 12 enter a conductive state.

Therefore, when power is supplied from the bit line 6 in this state, acurrent is provided from the second diffusion layer 19 (source) to thefirst diffusion layer (drain) via the channels 12, and further suppliedto the data line 4 via the MTJ element 3. At that time, the currentflows via the two channels 12 on the opposing sidewalls of the concaveportion 15. In other words, the current flow in the operating state ofthe memory cell 1 includes a current flow in a path x and a current flowin a path y, as shown in the figure.

This can effectively earn a channel width and provide a large amount ofcurrent, and also enables read of memory content and write ofinformation from and in the MTJ element 3.

The peripheral circuit portion has a configuration similar to a generalmemory apparatus. As shown in FIG. 3, a transistor constituted by asource 22, a gate electrode 20, and a drain 23 parallel to the siliconsubstrate 14 is formed. A connection wire 25 a is drawn from the source22. A connection wire 25 b is drawn from the drain 23. Each transistoris electrically isolated by element isolation regions 13. On the lowerportion of the element isolation region 13, a field isolation layer 11in which a silicon oxide film or the like is embedded is formed.

4. Method of Manufacturing Memory Cell of Embodiment

Hereinafter, a method of manufacturing a memory cell according to theembodiment will be described with reference to FIGS. 5 to 15 and FIG. 3.

FIG. 5 is a diagram showing a layer structure in a state where anisolation region of each cell of the memory cell according to theembodiment is formed.

Part A of FIG. 5 is a diagram of the memory cell 1 according to theembodiment when viewed from the top. Here, a part excerpted from FIG. 2is shown, and a portion to be the bit line 6 in a horizontal directionand portions to be the word lines 2 are shown. As described above, thememory cell 1 is formed at a center position of an intersection of theword line 2 and the bit line 6.

Part B of FIG. 5 shows a cross-sectional diagram taken along the linea-a. As shown in part B of FIG. 5, first, in the bottom portion of thesilicon substrate 14 that is to be the first diffusion layer 16 in thefuture, the field isolation layers 11 are formed by ion implantation soas to electrically isolate each memory cell 1 at a position having thedepth of approximately 200 to 400 nm, for example. The field isolationlayer 11 is formed of a silicon oxide film or the like. In the casewhere a silicon oxide film is formed, oxygen is injected into thesilicon substrate 14 at high energy and high density, and then heattreatment is performed. Thus, a silicon oxide film can be formed in thedepth of the silicon substrate 14.

As shown in a bird's eye view of part C of FIG. 5, the element isolationregion 13 is formed in a portion other than the silicon substrate 14immediately below a portion to be the bit line 6 in the future. Thefield isolation layer 11 is formed in the lower portion of the elementisolation region 13. The field isolation layer 11 is constituted by asilicon oxide film or the like.

By the above procedure, the element isolation regions 13 of theperipheral circuit portion can also be formed at the same time.

In description on subsequent manufacturing processes, part B of eachfigure shows an a-a cross section of part A thereof. In other words,part B of FIG. 6 to part B of FIG. 11 and part B of FIG. 14 to part B ofFIG. 16 show a-a cross sections of part A of FIG. 6 to part A of FIG. 11and part A of FIG. 14 to part A of FIG. 16, respectively, as in the caseof FIG. 5.

FIG. 6 is a diagram showing a layer structure in a state where agroove-shaped concave portion 15 of the memory cell according to theembodiment is formed. After the steps described in FIG. 5, the concaveportion 15 is formed.

As shown in part B of FIG. 6, the silicon substrate 14 and the fieldisolation layers 11 are processed by RIE (Reactive Ion Etching) to beformed into the shape of wiring lines in the vertical direction thatwill be the word lines 2, thus forming groove-shaped concave portions15. Almost the centers of the sidewall portions on both sides of thesilicon substrate 14 in each groove-shaped concave portion become thechannels 12 of the access transistor 5 that will be formed in asubsequent step.

As shown in a bird's eye view of part C of FIG. 6, the concave portion15 and the element isolation region 13 are in an intersectingrelationship.

FIG. 7 is a diagram showing a layer structure in a state where a firstdiffusion layer of the memory cell according to the embodiment isformed.

As shown in part B of FIG. 7, a first diffusion layer 16 is formed inthe bottom portion of the concave portion 15 by ion implantation. Thisportion corresponds to a portion to be one diffusion layer (drain) ofthe access transistor 5. Those diffusion layers are electricallyisolated from adjacent diffusion layers by the field isolation layers 11previously formed in FIG. 5. In the direction from the near side to thedeep side in the figure, the field isolation layer 11 and the elementisolation region 13 provide electrical isolation (insulation).

It should be noted that, as shown in FIG. 8, it is also conceived toform sidewall protective films 17 on the inner sides of the concaveportion 15 of the memory cell 1. When the first diffusion layer 16 isformed by ion implantation in the bottom portion of the concave portion15, it is necessary to perform high-concentration injection of 1E15/cm²or more. The sidewall protective films 17 are formed to protect thesidewalls, which are to be the channels 12 later, from contamination ofthe ion implantation.

The sidewall protective films 17 shown in part B of FIG. 8 can beremoved by wet processing of preprocessing for gate oxidation of theaccess transistor 5, which is a later step. The formation of thesidewall protective films 17 is not necessarily an indispensable step inthe manufacture of the memory cell according to this embodiment.

FIG. 9 is a diagram showing a layer structure in a state where a gateelectrode is embedded in the memory cell according to the embodiment. Agate electrode 18 is embedded in the state formed in FIG. 7. Thestructure of FIG. 8 in which the sidewall protective films 17 are formedmay be used.

In order to embed the gate electrode 18, first, a gate insulating filmis formed on an interior wall of the concave portion 15, and then thegate electrode 18 is embedded along the groove-shaped concave portion15. At that time, it is desirable that the gate electrode 18 be kept ina lower position than the silicon substrate 14 on the both sides of thegate electrode 18 and the upper portion thereof be made flat. The gateelectrode 18 can be made using polysilicon or a metal electrodematerial, or a composite film of them. The word line 2 is connected tothe gate electrode 18.

As shown in a bird's eye view of part C of FIG. 9, the gate electrode 18is formed along the concave portion 15.

FIG. 10 is a diagram showing a layer structure in a state where a seconddiffusion layer of the memory cell according to the embodiment isformed.

As shown in part B of FIG. 10, a second diffusion layer 19 is formed inthe upper portion of the silicon substrate 14 by ion implantation. Thisportion corresponds to a portion to be the other diffusion layer(source) of the access transistor 5.

FIG. 11 is a diagram showing a layer structure in a state where thesecond diffusion layer 19 of the memory cell 1 according to theembodiment and a bit line connected thereto are formed. First, after aninterlayer film 35 is formed, bit contacts 30 are opened in the upperportion of the memory cell, so that the bit line 6 is wired. The bitcontacts 30 are opened and connected as normal contacts to the seconddiffusion layer 19. Thus, when a voltage is applied to the word line 2,the voltage is applied to the gate electrode 18 connected to the wordline 2, and the access transistor 5 corresponding thereto can provide acurrent from the bit line 6 to the first diffusion layer 16 on thebottom portion of the concave portion 15, with the wall surfaces on theboth sides of the gate electrode 18, that is, the sidewalls of theconcave portion 15 being as channels.

Before the bit line 6 is formed, in the peripheral circuit portion,transistors each having the structure described with reference to FIG. 3are formed. The forming method is the same as a manufacturing method fora normal MOS transistor.

FIG. 12 is a diagram showing a layer structure in a state where metalwires on the upper layer side of the memory cell according to theembodiment are formed. To the method for the metal wires, a wiringforming step used for a normal semiconductor memory device can beapplied as it is. After a necessary wiring structure is formed, theupper portion is made flat by CMP (chemical mechanical polishing) or thelike, to make a state in which wafer boding can be performed.

Here, metal wires 24 a to 24 g are power source wires. In general, themetal wires 24 a to 24 g are made of aluminum or Cu. The metal wires 24b to 24 d can be each used as a shunt or the like. Metal wires 25 a to25 c connect the wiring layers. In general, the metal wires 25 a to 25 care filled with tungsten.

FIG. 13 is a diagram schematically showing a procedure of bonding anintermediate laminated body 31 formed on one substrate to anothersubstrate and performing thinning so as to manufacture the memory cellaccording to the embodiment.

The intermediate laminated body 31 represents a structure portion thatis formed as a lamination on the silicon substrate 14 by theabove-mentioned procedure to FIG. 12.

The upper portion of the silicon substrate 14 on which the intermediatelaminated body 31 is formed is made flat, and another silicon substrate26 that serves as a support substrate for maintaining rigidity is bondedthereto (see the left part and the center part of FIG. 13). The siliconsubstrate 26 is a simple substrate on which a laminated structure is notparticularly formed.

After the silicon substrate 26 is bonded, the silicon substrate 14 ispolished from its back surface (surface on which the intermediatelaminated body 31 is not formed) to be thinned (see the right part).

In the present disclosure, thinning is performed up to approximately 0.5μm to 1.5 μm, for example.

For example, the technology used for a backside illumination imagesensor can be applied to the series of bonding/thinning step.

FIG. 14 is a diagram showing a layer structure in which a back contactopening 27A is formed from the first diffusion layer 16 of theintermediate laminated body 31 of the memory cell 1 according to theembodiment. As shown in FIG. 12, the metal wires 24 and the bondedsilicon substrate 26 for a support substrate are present on the upperportion of the bit line 6, but illustration thereof is omittedhereinafter in FIGS. 14, 15, and 16.

Further, the silicon substrate is replaced with the upper-part siliconsubstrate 26 omitted in the figure. Thus, in actual processes, processformulation proceeds on the basis of a wafer in an upside-down statewith respect to one shown in the figure.

After the back surface of the silicon substrate 14 is thinned, a backinsulating film is deposited, and a minute back contact opening 27A isformed, from the back surface, in the first diffusion layer 16previously formed. When the back contact opening 27A is formed, the RIEis stopped at a depth that enables sufficient contact to the firstdiffusion layer 16.

FIG. 15 is a diagram showing a layer structure in which insulatingprotective films 29 are formed on sidewalls of the back contact opening27A formed from the first diffusion layer 16 of the intermediatelaminated body 31 of the memory cell according to the embodiment.

The protective insulating films 29 are formed on the sidewalls of theback contact opening 27A previously formed. This can prevent the backcontact 27 that will be described later from short-circuiting with thesilicon substrate 14. If this insulation is insufficient, an operationfailure may occur or performance as the memory cell may be impaired.

After the above steps are performed, the structure shown in FIG. 3 isformed and the memory cell 1 is completed.

Namely, the back contact 27 as a conductor is disposed in the backcontact opening 27A, and connection is extracted from the back contact27. The MTJ element 3 is thus formed as a memory element electricallyconnected to the first diffusion layer 16 by the back contact 27.

The back contact 27 is conceived as a copper plug, a tungsten plug, orthe like. It is desirable that an electrical connection point from thefirst diffusion layer 16 be extracted at low resistance.

As described above, the back contact 27 has a relatively low aspectratio and is directly drawn from the first diffusion layer 16corresponding to the drain of the access transistor 5, and thusresistance that is about ¼ to ⅕ lower than that of a general structurecan be expected.

The formation of the MTJ element 3 is performed on the back, flatsilicon substrate. So, the structure that is easy to be processed isprovided. The data line 4 is disposed above the MTJ element 3. The dataline 4 only needs to be a wire running parallel to the bit line 6, anddoes not involve an increase in cell area. Further, after the MTJelement 3 is formed, process construction by low-heat processing isenabled, and characteristics of a memory element of the MTJ element 3after the MTJ element 3 is formed are not imparted.

By the procedure described above, the memory cell according to thisembodiment can be manufactured.

With the memory cell structure formed as described above according tothis embodiment, the access transistor 5 has the two opposing sidewallportions of the concave portion 15 as channels, and thus the channelwidth more than twice as large as a normal transistor can be ensured.This can increase a current-driving capability without causing anincrease in cell area. In order to increase coercive characteristics ofthe MTJ element 3, it is desirable to provide a relatively large currentat a low voltage. So, it is effective to increase a current-drivingcapability of the access transistor 5.

Further, in the transistor, a source-drain current path is formed in aperpendicular direction, the second diffusion layer 19 and the bit line6 are connected to each other, and the first diffusion layer 16 isconnected to the MTJ element 3 via one back contact 27.

Normally, the MTJ element has low heat resistance as a material. So, inthe step of manufacturing a cell structure, the heat treatment performedafter the MTJ element is formed is intended to be minimized. For thatreason, in various memory cell structures, the following technique isadopted: a transistor portion, a metal wire portion, and the like areformed, and then MTJ elements are formed thereon. However, by thistechnique, the connection from the transistor to the MTJ element isprovided via a large number of contacts. This increases a resistancevalue by the contacts. In the case of this embodiment, since the MTJelement 3 is formed on the back side of the silicon substrate 14 onwhich the access transistor 5 is formed, and the first diffusion layer16 is thus connected to the MTJ element 3 via one back contact 27, theresistance by the contacts is minimized, and this embodiment isadvantageous in terms of this point as well. Moreover, the MTJ element 3can be created in a step after the metal wire step, and the influence ofthe heat treatment on the MTJ element 3 can be minimized.

5. Modified Example

Hereinafter, a modified example of the memory cell structure accordingto the embodiment will be described with reference to FIG. 16. FIG. 16is a diagram showing a modified example of the memory cell structureaccording to the embodiment. An SOI (silicon on insulator) substrate 33is used instead of a normal silicon substrate.

The SOI substrate is a substrate having a structure in which SiO₂ isinserted between a silicon substrate and a surface Si layer. In general,the SOI substrate is said to be effective in improvement in operatingspeed and reduction in power consumption, because a parasiticcapacitance of a transistor can be reduced. Compared with a case ofusing a normal silicon substrate, it is said that improvement of 20% to30% in the operating speed and reduction of 50% or more in powerconsumption can be expected.

As shown in FIG. 16, the memory cell structure is substantially the sameas the memory cell structure manufactured using the normal siliconsubstrate 14. The memory cell structure of FIG. 16 is different in thatthe protective insulating films 29 (see FIG. 3) formed on the sidewallsof the back contact 27 are not present. In other words, in the case ofusing the SOI substrate 33, insulation between the memory cells 1 can beensured without the protective insulating films 29, and thus it isunnecessary to form the protective insulating films 29.

In the back contact 27, a contact smaller than a minimum design can beformed by the sidewall process. So, sidewalls 34 are formed at endportions in which the back contact 27 is narrowed.

Advantages in the case of using the SOI substrate 33 are as follows.

(a) In the normal silicon substrate 14, it is indispensable to form auniform thin silicon substrate 14 including the memory cell 1, whereasthis is not needed in the case of the SOI substrate.

(b) In the normal silicon substrate 14, the depth tends to be larger tosome extent due to a margin of a film thickness of the silicon substrateof the back contact 27, whereas the depth does not become larger in thecase of the SOI substrate.

(c) In the normal silicon substrate 14, it is difficult to stop RIE athigh accuracy at a position of the first diffusion layer 16 when a backcontact is opened, whereas the RIE can be stopped at high accuracy inthe case of the SOI substrate.

(d) In the normal silicon substrate 14, the protective insulating films29 are required on the sidewalls in order to prevent the back contact 27and the silicon substrate 14 from short-circuiting, whereas theprotective insulating films 29 are not required in the case of the SOIsubstrate.

As described above, in the case where the SOI substrate 33 is used,excellent advantages are exhibited. The method of manufacturing thememory cell is similar to the case of the normal silicon substrate 14.

The memory cell structure and the method of manufacturing the sameaccording to the embodiment described above are not limited to those forthe MRAM, and can be applied to a memory such as a DRAM.

It should be noted that the effects described herein are merelyexemplary ones and are not restrictive ones, and any other effects maybe produced.

It should be noted that the present technology can have the followingconfigurations.

(1) A memory cell structure, including:

a transistor that uses a first diffusion layer formed in a bottomportion of a concave portion formed by processing a silicon substrateinto a groove shape, and a second diffusion layer formed in upper endportions of two opposing sidewall portions of the concave portion, toform channels at portions between the first diffusion layer and thesecond diffusion layer in the two sidewall portions; and

a memory element that is disposed below the first diffusion layer,

the first diffusion layer being electrically connected to the memoryelement via a contact formed after the silicon substrate is thinned.

(2) The memory cell structure according to (1), in which

the first diffusion layer is electrically insulated by an insulatingfilm and a substrate concentration profile for each memory cell.

(3) The memory cell structure according to (1) or (2), in which

the contact has a structure insulated from the silicon substrate.

(4) The memory cell structure according to any one of (1) to (3), inwhich

the silicon substrate is an SOI substrate.

(5) The memory cell structure according to any one of (1) to (4), inwhich

the memory element is an MTJ element.

(6) A method of manufacturing a memory having a memory cell structureincluding a transistor and a memory element, the transistor using afirst diffusion layer formed in a bottom portion of a concave portionformed by processing a silicon substrate into a groove shape, and asecond diffusion layer formed in upper end portions of two opposingsidewall portions of the concave portion, to form channels at portionsbetween the first diffusion layer and the second diffusion layer in thetwo sidewall portions, the memory element being disposed below the firstdiffusion layer, the first diffusion layer being electrically connectedto the memory element via a contact formed after the silicon substrateis thinned,

the method including the step of forming an intermediate laminated bodyas a part of the memory cell structure by performing at least the stepsof:

forming field isolation layers at a predetermined depth of the siliconsubstrate;

forming the groove-shaped concave portion between the field isolationlayers;

forming the first diffusion layer in the bottom portion of the concaveportion;

forming the second diffusion layer in the upper end portions of thesidewall portions of the concave portion; and

forming a metal wire in an upper portion of the second diffusion layer.

(7) The method of manufacturing a memory according to (6), including thesteps of:

bonding another silicon substrate as a support substrate to the siliconsubstrate on which the intermediate laminated body is formed; and

thinning the silicon substrate.

(8) The method of manufacturing a memory according to (7), including thestep of

forming a contact from the first diffusion layer formed on the thinnedsilicon substrate.

(9) The method of manufacturing a memory according to (8), including thestep of

forming a memory element electrically connected to the first diffusionlayer by the contact.

(10) A memory apparatus, including:

a memory cell including a memory element that holds informationdepending on a magnetization state of a magnetic body; and

two types of wires mutually intersect and other types of wires,

the memory cell having a memory cell structure including

-   -   a transistor that uses a first diffusion layer formed in a        bottom portion of a concave portion formed by processing a        silicon substrate into a groove shape, and a second diffusion        layer formed in upper end portions of two opposing sidewall        portions of the concave portion, to form channels at portions        between the first diffusion layer and the second diffusion layer        in the two sidewall portions, and    -   the memory element that is disposed below the first diffusion        layer, the first diffusion layer being electrically connected to        the memory element via a contact formed after the silicon        substrate is thinned,

the memory element being provided to a current between the two types ofwires via the transistor.

DESCRIPTION OF SYMBOLS

-   1, 10 memory cell-   2 word line-   3 MTJ-   4 data line-   5 access transistor-   6 bit line-   7 capacitor-   11 field isolation layer-   12 channel-   13 element isolation region-   14, 26 silicon substrate-   15 concave portion-   16 diffusion layer-   17 sidewall protective film-   18, 20 gate electrode-   19 second diffusion layer-   27 back contact-   28 back insulating layer-   29 protective insulating film-   31 intermediate laminated body-   33 SOI substrate

1-10. (canceled)
 11. A memory device, comprising: a substrate; aplurality of memory cells configured to be located on the substrate,wherein each of the memory cells includes a memory element and atransistor; a plurality of word lines; a plurality of bit lines; and aplurality of data lines, wherein a first node of the transistor connectsto the memory element, each of the word lines connects to a gateelectrode of the transistor, each of the bit lines connects to a secondnode of the transistor and each of the data lines connects to the memoryelement.
 12. The memory device according to claim 11, wherein the gateelectrode of the transistor is a buried gate structure.
 13. The memorycell structure according to claim 12, wherein the silicon substrateincludes a concave portion to form the buried gate structure.
 14. Thememory cell structure according to claim 11, wherein the siliconsubstrate is an SOI substrate.
 15. The memory cell structure accordingto claim 11, wherein the memory element is an MTJ element.